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information furnished by analog devices is be lieved to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? 2003 analog devices, inc. all rights reserved. adg633 cmos 5 v/+5 v/+3 v triple spdt switch features 2 v to 6 v dual supply 2 v to 12 v single supply automotive temperature range C40 o c to +125 o c <0.2 na leakage currents 52 on resistance over full signal range rail-to-rail switching operation 16-lead chip scale/tssop packages typical power consumption <0.1 w ttl/cmos compatible inputs package upgrades to 74hc4053 and max4053/max4583 applications automotive applications automatic test equipment data acquisition systems battery powered systems communication systems audio and video signal routing relay replacement sample-and-hold systems industrial control systems functional block diagram general description the adg633 is a low voltage cmos device comprising three independently selectable spdt (single pole double throw) switches. they are fully specif ed for 5 v, +5 v, and +3 v supplies. the adg633 switches are turned on with a logic low (or high) on the appropriate control input. each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. an en input is used to enable or en input is used to enable or en disable the device. when disabled, all channels are switched off. these parts are designed on an enhanced process that pro- vides lower power dissipation yet gives high switching speeds. low power consumption and an operating supply range of 2 v to 12 v make the adg633 ideal for battery-powered portable instruments. all channels exhibit break-before-make switching action, preventing momentary shorting when switching chan- nels. all digital inputs have 0.8 v to 2.4 v logic thresholds, ensuring ttl/cmos logic compatibility when using single +5 v or dual 5 v supplies. the adg633 is available in small 16-lead tssop packages and 16-lead 4 mm 4 mm chip scale packages. product highlights 1. single- and dual-supply operation. the adg633 offers high performance and is fully specif ed and guaranteed with 5 v, +5 v and +3 v supply rails. 2. automotive temperature range C40 o c to +125 o c. 3. guaranteed break-before-make switching action. 4. low power consumption, typically <0.1 w. 5. small 16-lead tssop and 16-lead 4 mm 4 mm chip scale packages. s1b d1 s1a s2a d2 s2b s3a d3 s3b a0 a1 a2 en logic adg633 switches sho wn for a logic 1 input rev. 0
C2 C adg633Cspecifications b version y version C40 c C40 c parameter +25 c to +85 c to +125 c unit test conditions/comments analog switch analog signal range v ss v s s v to v ss t o v ss dd to v d d to v v v dd = +4.5 v, v ss = C4.5 v on resistance (r on ) 52 typ v s = 4.5 v, i s = 1 ma; 75 90 100 max test circuit 1 on resistance match between 0.8 typ channels ( r on ) 1.3 1.8 2 max v s = +3.5 v, i s = 1 ma on resistance flatness (r flat(on) on resistance flatness (r fla t(on) on resistance flatness (r ) 9 typ v dd = +5 v, v ss = C5 v; 12 13 14 max v s = 3 v, i s = 1 ma leakage currents v dd = +5.5 v, v ss = C5.5 v source off leakage i s (off) 0.005 na typ v d = 4.5 v, v s = 4.5 v; 0.2 5 na max test circuit 2 drain off leakage i d (off) 0.005 na typ v d = 4.5 v, v s = 4.5 v; 0.2 5 na max test circuit 3 channel on leakage i d , i s (on) 0.005 na typ v d = v s = 4.5 v; test circuit 4 0.2 5 na max digital inputs input high voltage, v inh 2.4 v min input low voltage, v inl 0.8 v max input current i inl or i inl or i inl inh 0.005 a typ v in = v inl or v inl or v inl inh 1 a max c in , digital input capacitance 2 pf typ dynamic characteristics 2 t trans 60 ns typ r l r l r = 300 l = 300 l , c l = 35 pf, l = 35 pf , l 90 110 130 ns max v s = 3 v; test circuit 5 t on ( en ) 70 ns typ r l r l r = 300 l = 300 l , c l = 35 pf, l = 35 pf , l 95 120 135 ns max v s = 3 v; test circuit 7 t off ( en ) 25 ns typ r l r l r = 300 l = 300 l , c l = 35 pf, l = 35 pf , l 40 45 50 ns max v s = 3 v; test circuit 7 break-before-make time delay, t bbm 40 ns typ r l r l r = 300 l = 300 l , c l = 35 pf, l = 35 pf , l 10 ns min v s1 = v s2 = 3 v; test circuit 6 charge injection 2 pc typ v s = 0 v, r s = 0 , 4 pc max c l = 1 nf; test circuit 8 l = 1 nf; t est circuit 8 l off isolation C90 db typ r l r l r = 50 l = 50 l , c l = 5 pf, l = 5 pf , l f = 1 mhz; test circuit 9 total harmonic distortion, thd + n 0.025 % typ r l r l r = 600 , 2 v p-p, f = 20 hz to 20 khz channel-to-channel crosstalk C90 db typ r l r l r = 50 l = 50 l , c l = 5 pf, l = 5 pf , l f = 1 mhz; test circuit 11 C3 db bandwidth 580 mhz typ r l r l r = 50 l = 50 l , c l = 5 pf; l = 5 pf; l test circuit 10 c s (off) 4 pf typ f = 1 mhz c d (off) 7 pf typ f = 1 mhz c d , c s (on) 12 pf typ f = 1 mhz power requirements v dd = +5.5 v, v ss = C5.5 v i dd 0.01 a typ digital inputs = 0 v or 5.5 v 1 a max i ss 0.01 a typ digital inputs = 0 v or 5.5 v 1 a max notes 1 temperature range is as follows: b version: C40c to +85c. y version: C40c to +125c. 2 guaranteed by design, not subject to production test. specif cations subject to change without notice. dual supply 1 (v dd = +5 v 10%, v ss = C5 v 10%, gnd = 0 v, unless otherwise noted.) rev. 0
adg633 C3 C single supply 1 (v dd = 5 v 10%, v ss = 0 v, gnd = 0 v, unless otherwise noted.) b version y version C40 c C40 c parameter +25 c to +85 c to +125 c unit test conditions/comments analog switch analog signal range 0 to v dd 0 to v d d 0 to v v v dd = 4.5 v, v ss = 0 v on resistance (r on ) 85 typ v s = 0 v to 4.5 v, i s = 1 ma; 150 160 200 max test circuit 1 on resistance match between 4.5 typ v s = +3.5 v, i s = 1 ma channels ( r on ) 8 9 10 max on resistance flatness (r flat(on) on resistance flatness (r fla t(on) on resistance flatness (r ) 13 14 16 typ v dd = 5 v, v ss = 0 v v s = 1.5 v to 4 v, i s = 1 ma leakage currents v dd = 5.5 v source off leakage i s (off) 0.005 na typ v s = 1 v/4.5 v, v d = 4.5 v/1 v; 0.2 5 na max test circuit 2 drain off leakage i d (off) 0.005 na typ v s = 1 v/4.5 v, v d = 4.5 v/1 v; 0.2 5 na max test circuit 3 channel on leakage i d , i s (on) 0.005 na typ v s = v d = 1 v or 4.5 v; test circuit 4 0.2 5 na max digital inputs input high voltage, v inh 2.4 v min input low voltage, v inl inl inl 0.8 v max input current i inl or i inl or i inl inh 0.005 a typ v in = v inl or v inl or v inl inh 1 a max c in , digital input capacitance 2 pf typ dynamic characteristics 2 t trans 100 ns typ r l r l r = 300 l = 300 l , c l = 35 pf, l = 35 pf , l 150 190 220 ns max v s = 3 v; test circuit 5 t on ( en ) 100 ns typ r l r l r = 300 l = 300 l , c l = 35 pf, l = 35 pf , l 150 190 220 ns max v s = 3 v; test circuit 7 t off ( en ) 25 ns typ r l r l r = 300 l = 300 l , c l = 35 pf, l = 35 pf , l 35 45 50 ns max v s = 3 v; test circuit 7 break-before-make time delay, t bbm 90 ns typ r l r l r = 300 l = 300 l , c l = 35 pf, l = 35 pf , l 10 ns min v s1 = v s2 = 3 v; test circuit 6 charge injection 0.5 pc typ v s = 2.5 v, r s = 0 , c l = 1 nf; l = 1 nf; l 1 pc max test circuit 8 off isolation C90 db typ r l r l r = 50 l = 50 l , c l = 5 pf, f = 1 mhz; l = 5 pf , f = 1 mhz; l test circuit 9 channel-to-channel crosstalk C90 db typ r l r l r = 50 l = 50 l , c l = 5 pf, f = 1 mhz; l = 5 pf , f = 1 mhz; l test circuit 11 C3 db bandwidth 520 mhz typ r l r l r = 50 l = 50 l , c l = 5 pf; l = 5 pf; l test circuit 10 c s (off) 5 pf typ f = 1 mhz c d (off) 8 pf typ f = 1 mhz c d , c s (on) 12 pf typ f = 1 mhz power requirements v dd = 5.5 v i dd 0.01 a typ digital inputs = 0 v or 5.5 v 1 a max notes 1 temperature range is as follows: b version: C40c to +85c. y version: C40c to +125c. 2 guaranteed by design, not subject to production test. specif cations subject to change without notice. rev. 0
C4 C adg633Cspecifications single supply 1 (v dd = 2.7 v to 3.6 v, v ss = 0 v, gnd = 0 v, unless otherwise noted.) b version y version C40 c C40 c parameter +25 c to +85 c to +125 c unit test conditions/comments analog switch analog signal range 0 to v dd 0 to v d d 0 to v v v dd = 2.7 v, v ss = 0 v on resistance (r on ) 185 typ v s = 0 v to 2.7 v, i s = 0.1 ma; 300 350 400 max test circuit 1 on resistance match between 2 typ v s = +1.5 v, i s = 0.1 ma channels ( r on ) 4.5 6 7 max leakage currents v dd = 3.3 v source off leakage i s (off) 0.005 na typ v s = 1 v/3 v, v d = 3 v/1 v; 0.2 5 na max test circuit 2 drain off leakage i d (off) 0.005 na typ v s = 1 v/3 v, v d = 3 v/1 v; 0.2 5 na max test circuit 3 channel on leakage i d , i s (on) 0.005 na typ v s = v d = 1 v or 3 v; test circuit 4 0.2 5 na max digital inputs input high voltage, v inh 2.0 v min input low voltage, v inl inl inl 0.5 v max input current i inl or i inl or i inl inh 0.005 a typ v in = v inl or v inl or v inl inh 1 a max c in , digital input capacitance 2 pf typ dynamic characteristics 2 t trans 170 ns typ r l r l r = 300 l = 300 l , c l = 35 pf, l = 35 pf , l 300 370 400 ns max v s = 1.5 v; test circuit 5 t on ( en ) 200 ns typ r l r l r = 300 l = 300 l , c l = 35 pf, l = 35 pf , l 310 380 420 ns max v s = 1.5 v; test circuit 7 t off ( en ) 30 ns typ r l r l r = 300 l = 300 l , c l = 35 pf, l = 35 pf , l 40 55 75 ns max v s = 1.5 v; test circuit 7 break-before-make time delay, t bbm 180 ns typ r l r l r = 300 l = 300 l , c l = 35 pf, l = 35 pf , l 10 ns min v s1 = v s2 = 1.5 v; test circuit 6 charge injection 1 pc typ v s = 1.5 v, r s = 0 , c l = 1 nf; l = 1 nf; l 2 pc max test circuit 8 off isolation C90 db typ r l r l r = 50 l = 50 l , c l = 5 pf, f = 1 mhz; l = 5 pf , f = 1 mhz; l test circuit 9 channel-to-channel crosstalk C90 db typ r l r l r = 50 l = 50 l , c l = 5 pf, f = 1 mhz; l = 5 pf , f = 1 mhz; l test circuit 11 C3 db bandwidth 500 mhz typ r l r l r =50 l =50 l , c l = 5 pf; l = 5 pf; l test circuit 10 c s (off) 5 pf typ f = 1 mhz c d (off) 8 pf typ f = 1 mhz c d , c s (on) 12 pf typ f = 1 mhz power requirements v dd = 3.3 v i dd 0.01 a typ digital inputs = 0 v or 3.3 v 1 a max notes 1 temperature range is as follows: b version: C40c to +85c. y version: C40c to +125c. 2 guaranteed by design, not subject to production test. specif cations subject to change without notice. rev. 0
adg633 ?5? absolute maximum ratings 1 (t a = 25c, unless otherwise noted.) v dd to v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 v v dd to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . ?0.3 v to +13 v v ss to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 v to ?6.5 v analog inputs 2 . . . . . . . . . . . . . . . . . .v ss ? 0.3 v to v dd + 0.3 v digital inputs 2 . . . . . . . . . . . . . . . . gnd ? 0.3 v to v dd + 0.3 v or 10 ma, whichever occurs ? rst p eak current, s or d . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 ma (pulsed at 1 ms, 10% duty cycle max) continuous current, s or d . . . . . . . . . . . . . . . . . . . . . 20 ma operating temperature range automotive (y version) . . . . . . . . . . . . . . . ?40c to +125c industrial (b version) . . . . . . . . . . . . . . . . . . ?40c to +85c storage temperature range . . . . . . . . . . . . . . ?65c to +150c pin configurations tssop top view (not to scale) 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 s2b s2a s3b d3 s3a v ss en gnd v dd d2 d1 s1b s1a a0 a1 a2 adg633 8 lfcsp adg633 top view (not to scale) 11 9 8 7 6 5 4 3 2 1 12 13 14 15 16 10 s3b v ss a1 s1a d1 s1b en s3a d3 d2 v dd s2a s2b a2 gnd a0 ordering guide model temperature range package description package option adg633yru ?40c to +125c thin shrink small outline package (tssop) ru-16 adg633ycp ?40c to +85c chip scale package (lfcsp) cp-16 junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150c ja thermal impedance, 16-lead tssop . . . . . . . . 150.4c/w ja thermal impedance (4-layer board), 16-lead lfcsp . . . . . . . . . . . . . . . . . . . . . . . . . . . 70c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . 215c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220c esd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 kv notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this speci? cation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. only one absolute maximum rating may be applied at any one time. 2 overvoltages at a x , en , s, or d will be clamped by internal diodes. current should be limited to the maximum ratings given. ta b le i. adg633 truth table a2 a1 a0 en switch condition x x x 1 none 0 0 0 0 d1?s1a, d2?s2a, d3?s3a 0 0 1 0 d1?s1b, d2?s2a, d3?s3a 0 1 0 0 d1?s1a, d2?s2b, d3?s3a 0 1 1 0 d1?s1b, d2?s2b, d3?s3a 1 0 0 0 d1?s1a, d2?s2a, d3?s3b 1 0 1 0 d1?s1b, d2?s2a, d3?s3b 1 1 0 0 d1?s1a, d2?s2b, d3?s3b 1 1 1 0 d1?s1b, d2?s2b, d3?s3b x = don?t care caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily ac cu mu late on the human body and test equipment and can discharge without detection. although the adg633 features proprietary esd pro tec tion circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd pre cau tions are rec om mend ed to avoid per for mance deg ra da tion or loss of functionality. rev. 0
adg633 C6 C terminology parameter def nition v dd most positive power supply potential. v ss most negative power supply potential. i dd positive supply current. i ss negative supply current. gnd ground (0 v) reference. s source terminal. may be an input or output. d drain terminal. may be an input or output. a x logic control input. en active low digital input. when high, device is disabled and all switches are off. when low, a x logic inputs determine on switches. v d , v s analog voltage on terminals d, s. r on ohmic resistance between d and s. r on on resistance match between any two channels, i.e., r on max C r on min. r flat(on) r fla t(on) r flatness is def ned as the difference between the maximum and minimum value of on resistance as measured over the specif ed analog signal range. i s (off) source leakage current with the switch off. i d (off) drain leakage current with the switch off. i d , i s (on) channel leakage current with the switch on. v inl maximum input voltage for logic 0. v inh minimum input voltage for logic 1. i inl , i inh input current of the digital input. c s (off) off switch source capacitance. measured with reference to ground. c d (off) off switch drain capacitance. measured with reference to ground. c d ,c s (on) on switch capacitance. measured with reference to ground. c in digital input capacitance. t on ( en ) delay between applying the digital control input and the output switching on. see test circuit 7. t off ( en ) delay between applying the digital control input and the output switching off. t bbm on time, measured between 80% points of both switches when switching from one address state to another. charge injection a measure of the glitch impulse transferred from the digital input to the analog output during switching. off isolation a measure of unwanted signal coupling through an off switch. crosstalk a measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. bandwidth the frequency at which the output is attenuated by 3 db. on response the frequency response of the on switch. insertion loss the loss due to the on resistance of the switch. rev. 0
typical performance characteristicsCadg633 C7 C 0 200 150 100 50 250 0 2 4 6 8 1 2 v d , v s C v on resistance C 10 t a = 25 c v dd = 2.7v v dd = 3v v dd = 3.3 v v dd = 4.5v v dd = 5v v dd = 5.5v v dd = 10v v dd = 12v tpc 2. on resistance vs. v d tpc 2. on resistance vs. v d tpc 2. on resistance vs. v (v s (v s (v ) for single supply 250 300 200 0 0.5 1 v d , v s C v on resistance C 1.5 2 3 2.5 150 100 50 0 v ss = 0v v dd = 3v +125 c +85 c +25 c C40 c tpc 5. on resistance vs. v d tpc 5. on resistance vs. v d tpc 5. on resistance vs. v (v s (v s (v ) for different temperatures (single supply) 12 14 10 C5 C4 C3 v s C v q in j C pc C2 C1 0 1 2 3 4 5 8 6 4 2 C2 0 C4 t a = 25 c v dd = 5v v ss = 0v v ss = 0v v dd = 3v v ss = C5v v dd = +5v tpc 8. charge injection vs. source voltage 90 100 80 C5.5 C3.5 C1.5 v d , v s C v on resistance C 0.5 2.5 4.5 70 60 50 40 30 20 10 0 t a = 25 c v dd , v ss = 5.5v v dd , v ss = 3.3v v dd , v ss = 5v v dd , v ss = 3v v dd , v ss = 4.5v v dd , v ss = 2.7v tpc 1. on resistance vs. v d tpc 1. on resistance vs. v d tpc 1. on resistance vs. v (v s (v s (v ) for dual supply 140 0 0.5 1 v d , v s C v on resistance C 1.5 2 2.5 3.5 4.5 5 120 100 80 60 40 20 0 3 4 v dd = 5v v ss = 0v +125 c +85 c +25 c C40 c tpc 4. on resistance vs. v d tpc 4. on resistance vs. v d tpc 4. on resistance vs. v (v s (v s (v ) for different temperatures (single supply) 1.0 1.5 0.5 0 2 0 4 0 temperature C c current C na 60 80 120 100 0 C0.5 C1.0 C1.5 i s , i d (off) i s , i d (on) v dd = 5v v ss = 0v v d = 4v v s = 1v v dd = 3v v ss = 0v v d = 2.4v v s = 1v tpc 7. leakage currents vs. temperature (single supply) 90 100 80 C5 C4 C3 v d , v s C v on resistance C C2 C1 0 2 4 5 70 60 50 40 30 20 10 0 1 3 v dd = 5v v ss = 5v +125 c +85 c +25 c C40 c tpc 3. on resistance vs. v d tpc 3. on resistance vs. v d tpc 3. on resistance vs. v (v s (v s (v ) for different temperatures (dual supply) 1.0 1.5 0.5 0 2 0 4 0 temperature C c current C na 60 80 120 100 0 C0.5 C1.0 C1.5 v dd = +5v v ss = C5v v d = 4v v s = 4v i s (off) i d (off) i s , i d (on) tpc 6. leakage currents vs. temperature (dual supply) 90 100 t on t off 80 C40 C20 0 temperature C c time C ns 20 40 60 80 100 120 70 60 50 40 30 20 10 0 v dd = +5v v ss = C5v tpc 9. t on /t off times vs. temperature off t imes vs. t emperature off (dual supply) rev. 0
C8 C adg633 ??? ??? ??? ? ??? ??? ?? ?? ?????????????? ? ? ?????????? ?? ?? ??? ??? ??? ??? ?? ? ? ??? ? ?? ????? ? ?? ????? ? ?? ????? ? ?? ????? ? ?? ????? ? ?? tpc 10. t on /t off times vs. off t imes vs. off temperature (single supply) C30 C70 C110 0 C50 C90 C130 100k 1m 10m 100m C40 C80 C120 C10 C60 C100 C20 frequency C hz db v dd = C5v v ss = +5v t a = 25 c tpc 1 3. crosstalk vs. f requency 0 2.5 2.0 1.5 1.0 3.0 0 2 4 6 8 10 12 0.5 v dd C v logic threshold voltage C v tpc 16. logic level threshold vs. v dd tpc 16. logic level threshold vs. v dd tpc 16. logic level threshold vs. v 100k 1m 10m 100m 0 C10 frequency C hz db C8 C6 C4 C2 v dd = +5v v ss = C5v t a = 25 c tpc 11. on response vs. frequency ??? ?? ?? ??? ?????????????? ??????????? ? ??? ??? ?? ?? ??? ?? ? ?? ? ??? ???? ?? ??? ? ?????????? ? ?? ?????? ? ?? ?????? ? ? ????? ? ? tpc 14. thd + noise 100k 1m 10m 100m C40 C80 C120 0 C60 C100 C20 frequency C hz db v dd = +5v v ss = C5v t a = 25 c tpc 12. off isolation vs. frequency 100 1 0.01 10000 10 0.1 1000 0 2 4 6 8 10 1 2 v ss = 0v v dd = 12v v dd = 5v v dd = 3v v(/en) C v i dd C a tpc 15. v dd tpc 15. v dd tpc 15. v current vs. logic level dd cur rent vs. l ogic l evel dd rev. 0
adg633 C9 C test circuits i ds v1 s d v s r on = v1/i ds test circuit 1. on resistance s d a a i s (off) v s v d i s (off) test circuit 2. i s test circuit 2. i s test circuit 2. i (off) 90% 90% 50% 50% v out address drive (v in ) t transitio n t transition 3v 0v v dd v ss v s1a v out v in a2 a1 a0 en gn d s1a s1b d adg 633 v dd v ss 50 r l 300 0.1 f 0.1 f c l 35pf v s1b test circuit 5. transition time, t transition ? ??? ? ?? ? ?? ? ? ? ??? ? ?? ?? ?? ?? en ?? ? ??? ??? ?? ??? ??? ??? ?? ?? ? ??? ??? ??????? ???????? ?? ? ? ?? ? ?? ?? ? ? ? ??? ? ? ? ???? ??? ? ? ??? ? ? test circuit 6. break-before-make delay, t bbm test circuit 6. break-before-make delay, t bbm test circuit 6. break-before-make delay, t s d a v d nc i d (off) test circuit 3. i d test circuit 3. i d test circuit 3. i (off) ? ?? ??? ? ? ? ? ?? ? ? ??? ?? ? en ? ? ? ?? ??? ? ?? ? ?? test circuit 4. i d test circuit 4. i d test circuit 4. i (on) rev. 0
adg633 C10 C ? ? ? ??? ?? ? ?? ?? ?? en ??? ??? ??? ?? ? ?? ??? ??? ? ? ??? ? ? ? ???? ? ?? ? ?? ? ?? ? ?? ? ?? ? ? en ? ???? ? ??? ??? ?? ?? ? ? ?? ?????? ???????? ?? ? ?????? ? ??? ? ? en ? ? ???? ? ??? ? ? ??? ? ? test circuit 7. enable delay, t on ( en ( en ( ), t off ( off ( off en ( en ( ) ?? ?? ?? en ??? ? ??? ??? ? ? ??? ?? ?? ? ??? ??????????? ?? ?? ? ? ??? ??? ? ? ? ? ? ? ? ??? ? ? ??? ? ?? ? ?? ? ? ? ?? ? ? ? ? ??? ? ?? test circuit 8. charge injection v dd v ss a2 a1 a0 zc gnd s d 50 v v out v s logic 1 v dd v ss 0.1 f 0.1 f network analyzer 50 v r l 50 v off isolation = 20 log v out v s test circuit 9. off isolation v dd v ss a2 a1 a0 zc gnd sa da 0.1 f v out db 50 v v s adg 633 crosstalk = 20 lo g v out v s v dd v ss 0.1 f r l 50 v network analyzer network analyzer 50 v test circuit 11. channel-to-channel crosstalk v dd v ss a2 a1 a0 zc gn d s d insertion loss = 20 log v out with switch v out without switch r l 50 v v out 50 v v s v dd v ss 0.1 f 0.1 f network analyzer test circuit 10. bandwidth rev. 0
adg633 C11 C outline dimensions 16-lead thin shrink small outline package [tssop] (ru-16) dimensions shown in millimeters 16 9 8 1 pin 1 seating plane 8 0 4.50 4.40 4.30 6.40 bs c 5.10 5.00 4.90 0.65 bs c 0.15 0.05 1.20 ma x 0.20 0.09 0.75 0.60 0.45 0.30 0.19 coplanarit y 0.10 compliant to jedec standards mo-153ab 16-lead frame chip scale package [lfcsp] 4 mm 4 mm body (cp-16) dimensions shown in millimeters 16 5 13 8 9 12 1 4 bo tt om view 2.25 1.70 0.75 0.75 0.55 0.35 0.65 bs c 1.95 bs c 0.38 0.30 0.23 12 ma x 0.20 re f seating plane pin 1 indicator to p view 4.0 bsc sq 3.75 bsc sq 0.60 ma x 0.60 ma x 0.05 ma x 0.02 nom 1.00 ma x 0.65 nom compliant to jedec standards mo-220-vggc pin 1 indica to r 1.00 0.90 0.80 coplanarit y 0.08 sq rev. 0
c03275C0C2/03(0) printed in u.s.a. C12 C

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